func GNUSyntax(inst Inst) string
GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the RISC-V Instruction Set Manual. See https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string
GoSyntax returns the Go assembler syntax for the instruction. The syntax was originally defined by Plan 9. The pc is the program counter of the instruction, used for expanding PC-relative addresses into absolute ones. The symname function queries the symbol table for the program being disassembled. Given a target address it returns the name and base address of the symbol containing the target, if any; otherwise it returns "", 0. The reader text should read from the text segment using text addresses as offsets; it is used to display pc-relative loads as constant loads.
An Arg is a single instruction argument.
type Arg interface {
String() string
}
An Args holds the instruction arguments. If an instruction has fewer than 6 arguments, the final elements in the array are nil.
type Args [6]Arg
A CSR is a single control and status register. Use stringer to generate CSR match table.
type CSR uint16
const (
// Control status register
USTATUS CSR = 0x0000
FFLAGS CSR = 0x0001
FRM CSR = 0x0002
FCSR CSR = 0x0003
UIE CSR = 0x0004
UTVEC CSR = 0x0005
UTVT CSR = 0x0007
VSTART CSR = 0x0008
VXSAT CSR = 0x0009
VXRM CSR = 0x000a
VCSR CSR = 0x000f
USCRATCH CSR = 0x0040
UEPC CSR = 0x0041
UCAUSE CSR = 0x0042
UTVAL CSR = 0x0043
UIP CSR = 0x0044
UNXTI CSR = 0x0045
UINTSTATUS CSR = 0x0046
USCRATCHCSW CSR = 0x0048
USCRATCHCSWL CSR = 0x0049
SSTATUS CSR = 0x0100
SEDELEG CSR = 0x0102
SIDELEG CSR = 0x0103
SIE CSR = 0x0104
STVEC CSR = 0x0105
SCOUNTEREN CSR = 0x0106
STVT CSR = 0x0107
SSCRATCH CSR = 0x0140
SEPC CSR = 0x0141
SCAUSE CSR = 0x0142
STVAL CSR = 0x0143
SIP CSR = 0x0144
SNXTI CSR = 0x0145
SINTSTATUS CSR = 0x0146
SSCRATCHCSW CSR = 0x0148
SSCRATCHCSWL CSR = 0x0149
SATP CSR = 0x0180
VSSTATUS CSR = 0x0200
VSIE CSR = 0x0204
VSTVEC CSR = 0x0205
VSSCRATCH CSR = 0x0240
VSEPC CSR = 0x0241
VSCAUSE CSR = 0x0242
VSTVAL CSR = 0x0243
VSIP CSR = 0x0244
VSATP CSR = 0x0280
MSTATUS CSR = 0x0300
MISA CSR = 0x0301
MEDELEG CSR = 0x0302
MIDELEG CSR = 0x0303
MIE CSR = 0x0304
MTVEC CSR = 0x0305
MCOUNTEREN CSR = 0x0306
MTVT CSR = 0x0307
MSTATUSH CSR = 0x0310
MCOUNTINHIBIT CSR = 0x0320
MHPMEVENT3 CSR = 0x0323
MHPMEVENT4 CSR = 0x0324
MHPMEVENT5 CSR = 0x0325
MHPMEVENT6 CSR = 0x0326
MHPMEVENT7 CSR = 0x0327
MHPMEVENT8 CSR = 0x0328
MHPMEVENT9 CSR = 0x0329
MHPMEVENT10 CSR = 0x032a
MHPMEVENT11 CSR = 0x032b
MHPMEVENT12 CSR = 0x032c
MHPMEVENT13 CSR = 0x032d
MHPMEVENT14 CSR = 0x032e
MHPMEVENT15 CSR = 0x032f
MHPMEVENT16 CSR = 0x0330
MHPMEVENT17 CSR = 0x0331
MHPMEVENT18 CSR = 0x0332
MHPMEVENT19 CSR = 0x0333
MHPMEVENT20 CSR = 0x0334
MHPMEVENT21 CSR = 0x0335
MHPMEVENT22 CSR = 0x0336
MHPMEVENT23 CSR = 0x0337
MHPMEVENT24 CSR = 0x0338
MHPMEVENT25 CSR = 0x0339
MHPMEVENT26 CSR = 0x033a
MHPMEVENT27 CSR = 0x033b
MHPMEVENT28 CSR = 0x033c
MHPMEVENT29 CSR = 0x033d
MHPMEVENT30 CSR = 0x033e
MHPMEVENT31 CSR = 0x033f
MSCRATCH CSR = 0x0340
MEPC CSR = 0x0341
MCAUSE CSR = 0x0342
MTVAL CSR = 0x0343
MIP CSR = 0x0344
MNXTI CSR = 0x0345
MINTSTATUS CSR = 0x0346
MSCRATCHCSW CSR = 0x0348
MSCRATCHCSWL CSR = 0x0349
MTINST CSR = 0x034a
MTVAL2 CSR = 0x034b
PMPCFG0 CSR = 0x03a0
PMPCFG1 CSR = 0x03a1
PMPCFG2 CSR = 0x03a2
PMPCFG3 CSR = 0x03a3
PMPADDR0 CSR = 0x03b0
PMPADDR1 CSR = 0x03b1
PMPADDR2 CSR = 0x03b2
PMPADDR3 CSR = 0x03b3
PMPADDR4 CSR = 0x03b4
PMPADDR5 CSR = 0x03b5
PMPADDR6 CSR = 0x03b6
PMPADDR7 CSR = 0x03b7
PMPADDR8 CSR = 0x03b8
PMPADDR9 CSR = 0x03b9
PMPADDR10 CSR = 0x03ba
PMPADDR11 CSR = 0x03bb
PMPADDR12 CSR = 0x03bc
PMPADDR13 CSR = 0x03bd
PMPADDR14 CSR = 0x03be
PMPADDR15 CSR = 0x03bf
HSTATUS CSR = 0x0600
HEDELEG CSR = 0x0602
HIDELEG CSR = 0x0603
HIE CSR = 0x0604
HTIMEDELTA CSR = 0x0605
HCOUNTEREN CSR = 0x0606
HGEIE CSR = 0x0607
HTIMEDELTAH CSR = 0x0615
HTVAL CSR = 0x0643
HIP CSR = 0x0644
HVIP CSR = 0x0645
HTINST CSR = 0x064a
HGATP CSR = 0x0680
TSELECT CSR = 0x07a0
TDATA1 CSR = 0x07a1
TDATA2 CSR = 0x07a2
TDATA3 CSR = 0x07a3
TINFO CSR = 0x07a4
TCONTROL CSR = 0x07a5
MCONTEXT CSR = 0x07a8
MNOISE CSR = 0x07a9
SCONTEXT CSR = 0x07aa
DCSR CSR = 0x07b0
DPC CSR = 0x07b1
DSCRATCH0 CSR = 0x07b2
DSCRATCH1 CSR = 0x07b3
MCYCLE CSR = 0x0b00
MINSTRET CSR = 0x0b02
MHPMCOUNTER3 CSR = 0x0b03
MHPMCOUNTER4 CSR = 0x0b04
MHPMCOUNTER5 CSR = 0x0b05
MHPMCOUNTER6 CSR = 0x0b06
MHPMCOUNTER7 CSR = 0x0b07
MHPMCOUNTER8 CSR = 0x0b08
MHPMCOUNTER9 CSR = 0x0b09
MHPMCOUNTER10 CSR = 0x0b0a
MHPMCOUNTER11 CSR = 0x0b0b
MHPMCOUNTER12 CSR = 0x0b0c
MHPMCOUNTER13 CSR = 0x0b0d
MHPMCOUNTER14 CSR = 0x0b0e
MHPMCOUNTER15 CSR = 0x0b0f
MHPMCOUNTER16 CSR = 0x0b10
MHPMCOUNTER17 CSR = 0x0b11
MHPMCOUNTER18 CSR = 0x0b12
MHPMCOUNTER19 CSR = 0x0b13
MHPMCOUNTER20 CSR = 0x0b14
MHPMCOUNTER21 CSR = 0x0b15
MHPMCOUNTER22 CSR = 0x0b16
MHPMCOUNTER23 CSR = 0x0b17
MHPMCOUNTER24 CSR = 0x0b18
MHPMCOUNTER25 CSR = 0x0b19
MHPMCOUNTER26 CSR = 0x0b1a
MHPMCOUNTER27 CSR = 0x0b1b
MHPMCOUNTER28 CSR = 0x0b1c
MHPMCOUNTER29 CSR = 0x0b1d
MHPMCOUNTER30 CSR = 0x0b1e
MHPMCOUNTER31 CSR = 0x0b1f
MCYCLEH CSR = 0x0b80
MINSTRETH CSR = 0x0b82
MHPMCOUNTER3H CSR = 0x0b83
MHPMCOUNTER4H CSR = 0x0b84
MHPMCOUNTER5H CSR = 0x0b85
MHPMCOUNTER6H CSR = 0x0b86
MHPMCOUNTER7H CSR = 0x0b87
MHPMCOUNTER8H CSR = 0x0b88
MHPMCOUNTER9H CSR = 0x0b89
MHPMCOUNTER10H CSR = 0x0b8a
MHPMCOUNTER11H CSR = 0x0b8b
MHPMCOUNTER12H CSR = 0x0b8c
MHPMCOUNTER13H CSR = 0x0b8d
MHPMCOUNTER14H CSR = 0x0b8e
MHPMCOUNTER15H CSR = 0x0b8f
MHPMCOUNTER16H CSR = 0x0b90
MHPMCOUNTER17H CSR = 0x0b91
MHPMCOUNTER18H CSR = 0x0b92
MHPMCOUNTER19H CSR = 0x0b93
MHPMCOUNTER20H CSR = 0x0b94
MHPMCOUNTER21H CSR = 0x0b95
MHPMCOUNTER22H CSR = 0x0b96
MHPMCOUNTER23H CSR = 0x0b97
MHPMCOUNTER24H CSR = 0x0b98
MHPMCOUNTER25H CSR = 0x0b99
MHPMCOUNTER26H CSR = 0x0b9a
MHPMCOUNTER27H CSR = 0x0b9b
MHPMCOUNTER28H CSR = 0x0b9c
MHPMCOUNTER29H CSR = 0x0b9d
MHPMCOUNTER30H CSR = 0x0b9e
MHPMCOUNTER31H CSR = 0x0b9f
CYCLE CSR = 0x0c00
TIME CSR = 0x0c01
INSTRET CSR = 0x0c02
HPMCOUNTER3 CSR = 0x0c03
HPMCOUNTER4 CSR = 0x0c04
HPMCOUNTER5 CSR = 0x0c05
HPMCOUNTER6 CSR = 0x0c06
HPMCOUNTER7 CSR = 0x0c07
HPMCOUNTER8 CSR = 0x0c08
HPMCOUNTER9 CSR = 0x0c09
HPMCOUNTER10 CSR = 0x0c0a
HPMCOUNTER11 CSR = 0x0c0b
HPMCOUNTER12 CSR = 0x0c0c
HPMCOUNTER13 CSR = 0x0c0d
HPMCOUNTER14 CSR = 0x0c0e
HPMCOUNTER15 CSR = 0x0c0f
HPMCOUNTER16 CSR = 0x0c10
HPMCOUNTER17 CSR = 0x0c11
HPMCOUNTER18 CSR = 0x0c12
HPMCOUNTER19 CSR = 0x0c13
HPMCOUNTER20 CSR = 0x0c14
HPMCOUNTER21 CSR = 0x0c15
HPMCOUNTER22 CSR = 0x0c16
HPMCOUNTER23 CSR = 0x0c17
HPMCOUNTER24 CSR = 0x0c18
HPMCOUNTER25 CSR = 0x0c19
HPMCOUNTER26 CSR = 0x0c1a
HPMCOUNTER27 CSR = 0x0c1b
HPMCOUNTER28 CSR = 0x0c1c
HPMCOUNTER29 CSR = 0x0c1d
HPMCOUNTER30 CSR = 0x0c1e
HPMCOUNTER31 CSR = 0x0c1f
VL CSR = 0x0c20
VTYPE CSR = 0x0c21
VLENB CSR = 0x0c22
CYCLEH CSR = 0x0c80
TIMEH CSR = 0x0c81
INSTRETH CSR = 0x0c82
HPMCOUNTER3H CSR = 0x0c83
HPMCOUNTER4H CSR = 0x0c84
HPMCOUNTER5H CSR = 0x0c85
HPMCOUNTER6H CSR = 0x0c86
HPMCOUNTER7H CSR = 0x0c87
HPMCOUNTER8H CSR = 0x0c88
HPMCOUNTER9H CSR = 0x0c89
HPMCOUNTER10H CSR = 0x0c8a
HPMCOUNTER11H CSR = 0x0c8b
HPMCOUNTER12H CSR = 0x0c8c
HPMCOUNTER13H CSR = 0x0c8d
HPMCOUNTER14H CSR = 0x0c8e
HPMCOUNTER15H CSR = 0x0c8f
HPMCOUNTER16H CSR = 0x0c90
HPMCOUNTER17H CSR = 0x0c91
HPMCOUNTER18H CSR = 0x0c92
HPMCOUNTER19H CSR = 0x0c93
HPMCOUNTER20H CSR = 0x0c94
HPMCOUNTER21H CSR = 0x0c95
HPMCOUNTER22H CSR = 0x0c96
HPMCOUNTER23H CSR = 0x0c97
HPMCOUNTER24H CSR = 0x0c98
HPMCOUNTER25H CSR = 0x0c99
HPMCOUNTER26H CSR = 0x0c9a
HPMCOUNTER27H CSR = 0x0c9b
HPMCOUNTER28H CSR = 0x0c9c
HPMCOUNTER29H CSR = 0x0c9d
HPMCOUNTER30H CSR = 0x0c9e
HPMCOUNTER31H CSR = 0x0c9f
HGEIP CSR = 0x0e12
MVENDORID CSR = 0x0f11
MARCHID CSR = 0x0f12
MIMPID CSR = 0x0f13
MHARTID CSR = 0x0f14
MENTROPY CSR = 0x0f15
)
func (i CSR) String() string
An Inst is a single instruction.
type Inst struct {
Op Op // Opcode mnemonic.
Enc uint32 // Raw encoding bits.
Args Args // Instruction arguments, in RISC-V mamual order.
Len int // Length of encoded instruction in bytes
}
func Decode(src []byte) (Inst, error)
Decode decodes the 4 bytes in src as a single instruction.
func (i Inst) String() string
A MemOrder is a memory order hint in fence instruction
type MemOrder uint8
func (memOrder MemOrder) String() string
An Op is a RISC-V opcode.
type Op uint16
const (
ADD Op
ADDI
ADDIW
ADDW
ADD_UW
AMOADD_D
AMOADD_D_AQ
AMOADD_D_AQRL
AMOADD_D_RL
AMOADD_W
AMOADD_W_AQ
AMOADD_W_AQRL
AMOADD_W_RL
AMOAND_D
AMOAND_D_AQ
AMOAND_D_AQRL
AMOAND_D_RL
AMOAND_W
AMOAND_W_AQ
AMOAND_W_AQRL
AMOAND_W_RL
AMOMAXU_D
AMOMAXU_D_AQ
AMOMAXU_D_AQRL
AMOMAXU_D_RL
AMOMAXU_W
AMOMAXU_W_AQ
AMOMAXU_W_AQRL
AMOMAXU_W_RL
AMOMAX_D
AMOMAX_D_AQ
AMOMAX_D_AQRL
AMOMAX_D_RL
AMOMAX_W
AMOMAX_W_AQ
AMOMAX_W_AQRL
AMOMAX_W_RL
AMOMINU_D
AMOMINU_D_AQ
AMOMINU_D_AQRL
AMOMINU_D_RL
AMOMINU_W
AMOMINU_W_AQ
AMOMINU_W_AQRL
AMOMINU_W_RL
AMOMIN_D
AMOMIN_D_AQ
AMOMIN_D_AQRL
AMOMIN_D_RL
AMOMIN_W
AMOMIN_W_AQ
AMOMIN_W_AQRL
AMOMIN_W_RL
AMOOR_D
AMOOR_D_AQ
AMOOR_D_AQRL
AMOOR_D_RL
AMOOR_W
AMOOR_W_AQ
AMOOR_W_AQRL
AMOOR_W_RL
AMOSWAP_D
AMOSWAP_D_AQ
AMOSWAP_D_AQRL
AMOSWAP_D_RL
AMOSWAP_W
AMOSWAP_W_AQ
AMOSWAP_W_AQRL
AMOSWAP_W_RL
AMOXOR_D
AMOXOR_D_AQ
AMOXOR_D_AQRL
AMOXOR_D_RL
AMOXOR_W
AMOXOR_W_AQ
AMOXOR_W_AQRL
AMOXOR_W_RL
AND
ANDI
ANDN
AUIPC
BCLR
BCLRI
BEQ
BEXT
BEXTI
BGE
BGEU
BINV
BINVI
BLT
BLTU
BNE
BSET
BSETI
CLZ
CLZW
CPOP
CPOPW
CSRRC
CSRRCI
CSRRS
CSRRSI
CSRRW
CSRRWI
CTZ
CTZW
CZERO_EQZ
CZERO_NEZ
C_ADD
C_ADDI
C_ADDI16SP
C_ADDI4SPN
C_ADDIW
C_ADDW
C_AND
C_ANDI
C_BEQZ
C_BNEZ
C_EBREAK
C_FLD
C_FLDSP
C_FSD
C_FSDSP
C_J
C_JALR
C_JR
C_LD
C_LDSP
C_LI
C_LUI
C_LW
C_LWSP
C_MV
C_NOP
C_OR
C_SD
C_SDSP
C_SLLI
C_SRAI
C_SRLI
C_SUB
C_SUBW
C_SW
C_SWSP
C_UNIMP
C_XOR
DIV
DIVU
DIVUW
DIVW
EBREAK
ECALL
FADD_D
FADD_H
FADD_Q
FADD_S
FCLASS_D
FCLASS_H
FCLASS_Q
FCLASS_S
FCVT_D_L
FCVT_D_LU
FCVT_D_Q
FCVT_D_S
FCVT_D_W
FCVT_D_WU
FCVT_H_L
FCVT_H_LU
FCVT_H_S
FCVT_H_W
FCVT_H_WU
FCVT_LU_D
FCVT_LU_H
FCVT_LU_Q
FCVT_LU_S
FCVT_L_D
FCVT_L_H
FCVT_L_Q
FCVT_L_S
FCVT_Q_D
FCVT_Q_L
FCVT_Q_LU
FCVT_Q_S
FCVT_Q_W
FCVT_Q_WU
FCVT_S_D
FCVT_S_H
FCVT_S_L
FCVT_S_LU
FCVT_S_Q
FCVT_S_W
FCVT_S_WU
FCVT_WU_D
FCVT_WU_H
FCVT_WU_Q
FCVT_WU_S
FCVT_W_D
FCVT_W_H
FCVT_W_Q
FCVT_W_S
FDIV_D
FDIV_H
FDIV_Q
FDIV_S
FENCE
FENCE_I
FEQ_D
FEQ_H
FEQ_Q
FEQ_S
FLD
FLE_D
FLE_H
FLE_Q
FLE_S
FLH
FLQ
FLT_D
FLT_H
FLT_Q
FLT_S
FLW
FMADD_D
FMADD_H
FMADD_Q
FMADD_S
FMAX_D
FMAX_H
FMAX_Q
FMAX_S
FMIN_D
FMIN_H
FMIN_Q
FMIN_S
FMSUB_D
FMSUB_H
FMSUB_Q
FMSUB_S
FMUL_D
FMUL_H
FMUL_Q
FMUL_S
FMV_D_X
FMV_H_X
FMV_W_X
FMV_X_D
FMV_X_H
FMV_X_W
FNMADD_D
FNMADD_H
FNMADD_Q
FNMADD_S
FNMSUB_D
FNMSUB_H
FNMSUB_Q
FNMSUB_S
FSD
FSGNJN_D
FSGNJN_H
FSGNJN_Q
FSGNJN_S
FSGNJX_D
FSGNJX_H
FSGNJX_Q
FSGNJX_S
FSGNJ_D
FSGNJ_H
FSGNJ_Q
FSGNJ_S
FSH
FSQ
FSQRT_D
FSQRT_H
FSQRT_Q
FSQRT_S
FSUB_D
FSUB_H
FSUB_Q
FSUB_S
FSW
JAL
JALR
LB
LBU
LD
LH
LHU
LR_D
LR_D_AQ
LR_D_AQRL
LR_D_RL
LR_W
LR_W_AQ
LR_W_AQRL
LR_W_RL
LUI
LW
LWU
MAX
MAXU
MIN
MINU
MUL
MULH
MULHSU
MULHU
MULW
OR
ORC_B
ORI
ORN
REM
REMU
REMUW
REMW
REV8
ROL
ROLW
ROR
RORI
RORIW
RORW
SB
SC_D
SC_D_AQ
SC_D_AQRL
SC_D_RL
SC_W
SC_W_AQ
SC_W_AQRL
SC_W_RL
SD
SEXT_B
SEXT_H
SH
SH1ADD
SH1ADD_UW
SH2ADD
SH2ADD_UW
SH3ADD
SH3ADD_UW
SLL
SLLI
SLLIW
SLLI_UW
SLLW
SLT
SLTI
SLTIU
SLTU
SRA
SRAI
SRAIW
SRAW
SRL
SRLI
SRLIW
SRLW
SUB
SUBW
SW
VAADDU_VV
VAADDU_VX
VAADD_VV
VAADD_VX
VADC_VIM
VADC_VVM
VADC_VXM
VADD_VI
VADD_VV
VADD_VX
VAND_VI
VAND_VV
VAND_VX
VASUBU_VV
VASUBU_VX
VASUB_VV
VASUB_VX
VCOMPRESS_VM
VCPOP_M
VDIVU_VV
VDIVU_VX
VDIV_VV
VDIV_VX
VFADD_VF
VFADD_VV
VFCLASS_V
VFCVT_F_XU_V
VFCVT_F_X_V
VFCVT_RTZ_XU_F_V
VFCVT_RTZ_X_F_V
VFCVT_XU_F_V
VFCVT_X_F_V
VFDIV_VF
VFDIV_VV
VFIRST_M
VFMACC_VF
VFMACC_VV
VFMADD_VF
VFMADD_VV
VFMAX_VF
VFMAX_VV
VFMERGE_VFM
VFMIN_VF
VFMIN_VV
VFMSAC_VF
VFMSAC_VV
VFMSUB_VF
VFMSUB_VV
VFMUL_VF
VFMUL_VV
VFMV_F_S
VFMV_S_F
VFMV_V_F
VFNCVT_F_F_W
VFNCVT_F_XU_W
VFNCVT_F_X_W
VFNCVT_ROD_F_F_W
VFNCVT_RTZ_XU_F_W
VFNCVT_RTZ_X_F_W
VFNCVT_XU_F_W
VFNCVT_X_F_W
VFNMACC_VF
VFNMACC_VV
VFNMADD_VF
VFNMADD_VV
VFNMSAC_VF
VFNMSAC_VV
VFNMSUB_VF
VFNMSUB_VV
VFRDIV_VF
VFREC7_V
VFREDMAX_VS
VFREDMIN_VS
VFREDOSUM_VS
VFREDUSUM_VS
VFRSQRT7_V
VFRSUB_VF
VFSGNJN_VF
VFSGNJN_VV
VFSGNJX_VF
VFSGNJX_VV
VFSGNJ_VF
VFSGNJ_VV
VFSLIDE1DOWN_VF
VFSLIDE1UP_VF
VFSQRT_V
VFSUB_VF
VFSUB_VV
VFWADD_VF
VFWADD_VV
VFWADD_WF
VFWADD_WV
VFWCVT_F_F_V
VFWCVT_F_XU_V
VFWCVT_F_X_V
VFWCVT_RTZ_XU_F_V
VFWCVT_RTZ_X_F_V
VFWCVT_XU_F_V
VFWCVT_X_F_V
VFWMACC_VF
VFWMACC_VV
VFWMSAC_VF
VFWMSAC_VV
VFWMUL_VF
VFWMUL_VV
VFWNMACC_VF
VFWNMACC_VV
VFWNMSAC_VF
VFWNMSAC_VV
VFWREDOSUM_VS
VFWREDUSUM_VS
VFWSUB_VF
VFWSUB_VV
VFWSUB_WF
VFWSUB_WV
VID_V
VIOTA_M
VL1RE16_V
VL1RE32_V
VL1RE64_V
VL1RE8_V
VL2RE16_V
VL2RE32_V
VL2RE64_V
VL2RE8_V
VL4RE16_V
VL4RE32_V
VL4RE64_V
VL4RE8_V
VL8RE16_V
VL8RE32_V
VL8RE64_V
VL8RE8_V
VLE16FF_V
VLE16_V
VLE32FF_V
VLE32_V
VLE64FF_V
VLE64_V
VLE8FF_V
VLE8_V
VLM_V
VLOXEI16_V
VLOXEI32_V
VLOXEI64_V
VLOXEI8_V
VLOXSEG2EI16_V
VLOXSEG2EI32_V
VLOXSEG2EI64_V
VLOXSEG2EI8_V
VLOXSEG3EI16_V
VLOXSEG3EI32_V
VLOXSEG3EI64_V
VLOXSEG3EI8_V
VLOXSEG4EI16_V
VLOXSEG4EI32_V
VLOXSEG4EI64_V
VLOXSEG4EI8_V
VLOXSEG5EI16_V
VLOXSEG5EI32_V
VLOXSEG5EI64_V
VLOXSEG5EI8_V
VLOXSEG6EI16_V
VLOXSEG6EI32_V
VLOXSEG6EI64_V
VLOXSEG6EI8_V
VLOXSEG7EI16_V
VLOXSEG7EI32_V
VLOXSEG7EI64_V
VLOXSEG7EI8_V
VLOXSEG8EI16_V
VLOXSEG8EI32_V
VLOXSEG8EI64_V
VLOXSEG8EI8_V
VLSE16_V
VLSE32_V
VLSE64_V
VLSE8_V
VLSEG2E16FF_V
VLSEG2E16_V
VLSEG2E32FF_V
VLSEG2E32_V
VLSEG2E64FF_V
VLSEG2E64_V
VLSEG2E8FF_V
VLSEG2E8_V
VLSEG3E16FF_V
VLSEG3E16_V
VLSEG3E32FF_V
VLSEG3E32_V
VLSEG3E64FF_V
VLSEG3E64_V
VLSEG3E8FF_V
VLSEG3E8_V
VLSEG4E16FF_V
VLSEG4E16_V
VLSEG4E32FF_V
VLSEG4E32_V
VLSEG4E64FF_V
VLSEG4E64_V
VLSEG4E8FF_V
VLSEG4E8_V
VLSEG5E16FF_V
VLSEG5E16_V
VLSEG5E32FF_V
VLSEG5E32_V
VLSEG5E64FF_V
VLSEG5E64_V
VLSEG5E8FF_V
VLSEG5E8_V
VLSEG6E16FF_V
VLSEG6E16_V
VLSEG6E32FF_V
VLSEG6E32_V
VLSEG6E64FF_V
VLSEG6E64_V
VLSEG6E8FF_V
VLSEG6E8_V
VLSEG7E16FF_V
VLSEG7E16_V
VLSEG7E32FF_V
VLSEG7E32_V
VLSEG7E64FF_V
VLSEG7E64_V
VLSEG7E8FF_V
VLSEG7E8_V
VLSEG8E16FF_V
VLSEG8E16_V
VLSEG8E32FF_V
VLSEG8E32_V
VLSEG8E64FF_V
VLSEG8E64_V
VLSEG8E8FF_V
VLSEG8E8_V
VLSSEG2E16_V
VLSSEG2E32_V
VLSSEG2E64_V
VLSSEG2E8_V
VLSSEG3E16_V
VLSSEG3E32_V
VLSSEG3E64_V
VLSSEG3E8_V
VLSSEG4E16_V
VLSSEG4E32_V
VLSSEG4E64_V
VLSSEG4E8_V
VLSSEG5E16_V
VLSSEG5E32_V
VLSSEG5E64_V
VLSSEG5E8_V
VLSSEG6E16_V
VLSSEG6E32_V
VLSSEG6E64_V
VLSSEG6E8_V
VLSSEG7E16_V
VLSSEG7E32_V
VLSSEG7E64_V
VLSSEG7E8_V
VLSSEG8E16_V
VLSSEG8E32_V
VLSSEG8E64_V
VLSSEG8E8_V
VLUXEI16_V
VLUXEI32_V
VLUXEI64_V
VLUXEI8_V
VLUXSEG2EI16_V
VLUXSEG2EI32_V
VLUXSEG2EI64_V
VLUXSEG2EI8_V
VLUXSEG3EI16_V
VLUXSEG3EI32_V
VLUXSEG3EI64_V
VLUXSEG3EI8_V
VLUXSEG4EI16_V
VLUXSEG4EI32_V
VLUXSEG4EI64_V
VLUXSEG4EI8_V
VLUXSEG5EI16_V
VLUXSEG5EI32_V
VLUXSEG5EI64_V
VLUXSEG5EI8_V
VLUXSEG6EI16_V
VLUXSEG6EI32_V
VLUXSEG6EI64_V
VLUXSEG6EI8_V
VLUXSEG7EI16_V
VLUXSEG7EI32_V
VLUXSEG7EI64_V
VLUXSEG7EI8_V
VLUXSEG8EI16_V
VLUXSEG8EI32_V
VLUXSEG8EI64_V
VLUXSEG8EI8_V
VMACC_VV
VMACC_VX
VMADC_VI
VMADC_VIM
VMADC_VV
VMADC_VVM
VMADC_VX
VMADC_VXM
VMADD_VV
VMADD_VX
VMANDN_MM
VMAND_MM
VMAXU_VV
VMAXU_VX
VMAX_VV
VMAX_VX
VMERGE_VIM
VMERGE_VVM
VMERGE_VXM
VMFEQ_VF
VMFEQ_VV
VMFGE_VF
VMFGT_VF
VMFLE_VF
VMFLE_VV
VMFLT_VF
VMFLT_VV
VMFNE_VF
VMFNE_VV
VMINU_VV
VMINU_VX
VMIN_VV
VMIN_VX
VMNAND_MM
VMNOR_MM
VMORN_MM
VMOR_MM
VMSBC_VV
VMSBC_VVM
VMSBC_VX
VMSBC_VXM
VMSBF_M
VMSEQ_VI
VMSEQ_VV
VMSEQ_VX
VMSGTU_VI
VMSGTU_VX
VMSGT_VI
VMSGT_VX
VMSIF_M
VMSLEU_VI
VMSLEU_VV
VMSLEU_VX
VMSLE_VI
VMSLE_VV
VMSLE_VX
VMSLTU_VV
VMSLTU_VX
VMSLT_VV
VMSLT_VX
VMSNE_VI
VMSNE_VV
VMSNE_VX
VMSOF_M
VMULHSU_VV
VMULHSU_VX
VMULHU_VV
VMULHU_VX
VMULH_VV
VMULH_VX
VMUL_VV
VMUL_VX
VMV1R_V
VMV2R_V
VMV4R_V
VMV8R_V
VMV_S_X
VMV_V_I
VMV_V_V
VMV_V_X
VMV_X_S
VMXNOR_MM
VMXOR_MM
VNCLIPU_WI
VNCLIPU_WV
VNCLIPU_WX
VNCLIP_WI
VNCLIP_WV
VNCLIP_WX
VNMSAC_VV
VNMSAC_VX
VNMSUB_VV
VNMSUB_VX
VNSRA_WI
VNSRA_WV
VNSRA_WX
VNSRL_WI
VNSRL_WV
VNSRL_WX
VOR_VI
VOR_VV
VOR_VX
VREDAND_VS
VREDMAXU_VS
VREDMAX_VS
VREDMINU_VS
VREDMIN_VS
VREDOR_VS
VREDSUM_VS
VREDXOR_VS
VREMU_VV
VREMU_VX
VREM_VV
VREM_VX
VRGATHEREI16_VV
VRGATHER_VI
VRGATHER_VV
VRGATHER_VX
VRSUB_VI
VRSUB_VX
VS1R_V
VS2R_V
VS4R_V
VS8R_V
VSADDU_VI
VSADDU_VV
VSADDU_VX
VSADD_VI
VSADD_VV
VSADD_VX
VSBC_VVM
VSBC_VXM
VSE16_V
VSE32_V
VSE64_V
VSE8_V
VSETIVLI
VSETVL
VSETVLI
VSEXT_VF2
VSEXT_VF4
VSEXT_VF8
VSLIDE1DOWN_VX
VSLIDE1UP_VX
VSLIDEDOWN_VI
VSLIDEDOWN_VX
VSLIDEUP_VI
VSLIDEUP_VX
VSLL_VI
VSLL_VV
VSLL_VX
VSMUL_VV
VSMUL_VX
VSM_V
VSOXEI16_V
VSOXEI32_V
VSOXEI64_V
VSOXEI8_V
VSOXSEG2EI16_V
VSOXSEG2EI32_V
VSOXSEG2EI64_V
VSOXSEG2EI8_V
VSOXSEG3EI16_V
VSOXSEG3EI32_V
VSOXSEG3EI64_V
VSOXSEG3EI8_V
VSOXSEG4EI16_V
VSOXSEG4EI32_V
VSOXSEG4EI64_V
VSOXSEG4EI8_V
VSOXSEG5EI16_V
VSOXSEG5EI32_V
VSOXSEG5EI64_V
VSOXSEG5EI8_V
VSOXSEG6EI16_V
VSOXSEG6EI32_V
VSOXSEG6EI64_V
VSOXSEG6EI8_V
VSOXSEG7EI16_V
VSOXSEG7EI32_V
VSOXSEG7EI64_V
VSOXSEG7EI8_V
VSOXSEG8EI16_V
VSOXSEG8EI32_V
VSOXSEG8EI64_V
VSOXSEG8EI8_V
VSRA_VI
VSRA_VV
VSRA_VX
VSRL_VI
VSRL_VV
VSRL_VX
VSSE16_V
VSSE32_V
VSSE64_V
VSSE8_V
VSSEG2E16_V
VSSEG2E32_V
VSSEG2E64_V
VSSEG2E8_V
VSSEG3E16_V
VSSEG3E32_V
VSSEG3E64_V
VSSEG3E8_V
VSSEG4E16_V
VSSEG4E32_V
VSSEG4E64_V
VSSEG4E8_V
VSSEG5E16_V
VSSEG5E32_V
VSSEG5E64_V
VSSEG5E8_V
VSSEG6E16_V
VSSEG6E32_V
VSSEG6E64_V
VSSEG6E8_V
VSSEG7E16_V
VSSEG7E32_V
VSSEG7E64_V
VSSEG7E8_V
VSSEG8E16_V
VSSEG8E32_V
VSSEG8E64_V
VSSEG8E8_V
VSSRA_VI
VSSRA_VV
VSSRA_VX
VSSRL_VI
VSSRL_VV
VSSRL_VX
VSSSEG2E16_V
VSSSEG2E32_V
VSSSEG2E64_V
VSSSEG2E8_V
VSSSEG3E16_V
VSSSEG3E32_V
VSSSEG3E64_V
VSSSEG3E8_V
VSSSEG4E16_V
VSSSEG4E32_V
VSSSEG4E64_V
VSSSEG4E8_V
VSSSEG5E16_V
VSSSEG5E32_V
VSSSEG5E64_V
VSSSEG5E8_V
VSSSEG6E16_V
VSSSEG6E32_V
VSSSEG6E64_V
VSSSEG6E8_V
VSSSEG7E16_V
VSSSEG7E32_V
VSSSEG7E64_V
VSSSEG7E8_V
VSSSEG8E16_V
VSSSEG8E32_V
VSSSEG8E64_V
VSSSEG8E8_V
VSSUBU_VV
VSSUBU_VX
VSSUB_VV
VSSUB_VX
VSUB_VV
VSUB_VX
VSUXEI16_V
VSUXEI32_V
VSUXEI64_V
VSUXEI8_V
VSUXSEG2EI16_V
VSUXSEG2EI32_V
VSUXSEG2EI64_V
VSUXSEG2EI8_V
VSUXSEG3EI16_V
VSUXSEG3EI32_V
VSUXSEG3EI64_V
VSUXSEG3EI8_V
VSUXSEG4EI16_V
VSUXSEG4EI32_V
VSUXSEG4EI64_V
VSUXSEG4EI8_V
VSUXSEG5EI16_V
VSUXSEG5EI32_V
VSUXSEG5EI64_V
VSUXSEG5EI8_V
VSUXSEG6EI16_V
VSUXSEG6EI32_V
VSUXSEG6EI64_V
VSUXSEG6EI8_V
VSUXSEG7EI16_V
VSUXSEG7EI32_V
VSUXSEG7EI64_V
VSUXSEG7EI8_V
VSUXSEG8EI16_V
VSUXSEG8EI32_V
VSUXSEG8EI64_V
VSUXSEG8EI8_V
VWADDU_VV
VWADDU_VX
VWADDU_WV
VWADDU_WX
VWADD_VV
VWADD_VX
VWADD_WV
VWADD_WX
VWMACCSU_VV
VWMACCSU_VX
VWMACCUS_VX
VWMACCU_VV
VWMACCU_VX
VWMACC_VV
VWMACC_VX
VWMULSU_VV
VWMULSU_VX
VWMULU_VV
VWMULU_VX
VWMUL_VV
VWMUL_VX
VWREDSUMU_VS
VWREDSUM_VS
VWSUBU_VV
VWSUBU_VX
VWSUBU_WV
VWSUBU_WX
VWSUB_VV
VWSUB_VX
VWSUB_WV
VWSUB_WX
VXOR_VI
VXOR_VV
VXOR_VX
VZEXT_VF2
VZEXT_VF4
VZEXT_VF8
XNOR
XOR
XORI
ZEXT_H
)
func (op Op) String() string
NOTE: The actual Op values are defined in tables.go.
A Reg is a single register. The zero value denotes X0, not the absence of a register.
type Reg uint16
const (
// General-purpose registers
X0 Reg = iota
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
X17
X18
X19
X20
X21
X22
X23
X24
X25
X26
X27
X28
X29
X30
X31
// Floating point registers
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
// Vector registers
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
)
func (r Reg) String() string
A RegOffset is a register with offset value
type RegOffset struct {
OfsReg Reg
Ofs Simm
}
func (regofs RegOffset) String() string
A RegPtr is an address register with no offset
type RegPtr struct {
// contains filtered or unexported fields
}
func (regPtr RegPtr) String() string
A Simm is a signed immediate number
type Simm struct {
Imm int32 // 32-bit signed integer
Decimal bool // Print format of the immediate, either decimal or hexadecimal
Width uint8 // Actual width of the Simm
}
func (si Simm) String() string
An Uimm is an unsigned immediate number
type Uimm struct {
Imm uint32 // 32-bit unsigned integer
Decimal bool // Print format of the immediate, either decimal or hexadecimal
}
func (ui Uimm) String() string
A VType represents the vtype field of VSETIVLI and VSETVLI instructions
type VType uint32
func (vtype VType) String() string